The need for scaling metal-oxide-semiconductor (MOS) devices down to below 0.1 μm feature size in very-large-scale integrated (VLSI) circuits has been clearly indicated in the National Technology Road Map for Semiconductor Technology (1997 Edition), Semiconductor Industry Association, San Jose, Calif. For such circuits, silicon-on-insulator (SOI) MOS devices appear to be promising as described in SOI Technology: Materials to VLSI (2nd edition), Boston, Kluwer, 1997. Such materials are disadvantaged, however, in having a large dose of oxygen ions implanted through the top surface layer of a silicon wafer on which devices are fabricated.
An alternative method for fabricating SOI materials is disclosed in U.S. Pat. No. 5,374,564, issued Dec. 20, 1994 to Bruel and incorporated herein in its entirety. Instead of using ion implantation, an oxide layer is formed by oxidation of the top surface of a silicon wafer, protons are implanted through the oxidized surface, the implanted wafer is annealed to form a hydrogen micro-bubble layer beneath a thin surface layer, a stiffener silicon wafer is attached to the oxidized surface of the annealed wafer, and the resulting structure is heated to expand the micro-bubbles, thereby lifting off the top surface layer which remains attached to the stiffener wafer, forming an SOI wafer. It has been reported further, by K. Henttinen et al., “Mechanically induced Si layer transfer in hydrogen-implanted Si wafers”, Applied Physics Letters, Vol. 76, No. 17, 24 April 2000, that, after proton implantation beneath a top surface layer of a silicon wafer and annealing to form hydrogen bubbles, the surface layer can be mechanically lifted off by a stiffener wafer at relatively low temperatures.
Incorporated herein in their entirety are U.S. Pat. Nos. 5,198,371 and 5,633,174, issued to Li on Mar. 30, 1993 and May 27, 1997, respectively, disclosing a high-resistivity hydrogen bubble layer or defect layer under a thin surface layer of a silicon wafer after hydrogen implantation and annealing at high temperature. Termed “silicon-on-defect layer”, the surface layer was found to have improved semiconductor properties such as electron mobility. The structure of the hydrogen bubble or platelet layer is described by J. Grisolia et al., A transmission electron microscopy quantitative study of the growth kinetics of H platelets in Si”, Applied Physics Letters, Vol. 76, No. 7, 14 Feb. 2000.
Li, Jones, Coleman, Yi, Wallace and Anderson, “Properties of Silicon-on-Defect-Layer Material”, pp. 745-750 in Materials Research Society Proceedings, Vol. 396, David B Poker et al., Ed., Materials Research Society (MRS), Pittsburgh, Pa., 1996 report on high-temperature annealing after proton implantation resulting in conversion of a top surface layer on a high-resistivity layer from n-type to p-type, thereby forming a p-n junction at the high-resistivity layer. Furthermore, the p-type spreading resistivity was found to decrease steadily from the high-resistivity buried layer to a low resistivity at the surface of the wafer, lower than original wafer resistivity, and the n-type spreading resistivity to decrease steadily to its original value beneath the defect layer, as illustrated there at p. 747 in FIG. 1. The conversion from n-type to p-type by proton implantation in the top surface layer has been confirmed by data of Li, “New annealing processes and explanation for novel pn junctions formed by proton implantation”, Electronics Letters, Vol. 35, p. 133, 1997. Furthermore, as reported by Li in Nuclear Instruments and Methods in Physics Research B, Vol. 160, p. 190-193, Elsevier, 2000, when a p-type silicon wafer was implanted with protons and annealed, a high-resistivity bubble layer was formed beneath the surface, without affecting the type of the overlying surface layer.
Over prior SOI and silicon-on-defect-layer (SODL) device structures, the invention described below results in advantages which are particularly significant in ultra-large-scale integration (ULSI).